The present invention relates to an instruction prefetch system for an information processor which has an instruction buffer and which adopts the pipelining processing method.
In a conventional information processor with an instruction buffer, sequence control of instructions by pipelining is performed according to the following procedure: (i) an operand logic address register and an instruction buffer supplement (instruction prefetch) address register are selected by the selector, and a physical address is generated by a common physical address generator; and (ii) the common memory (main memory or the buffer memory) is accessed to selectively supply operand data to the execution stage and an instruction word to the instruction buffer, respectively. During the supplement (prefetch) of the instruction word into the instruction buffer, processing and transmission (to be referred to simply as "instruction fetch" hereinafter) for execution of an instruction fetched from the instruction buffer cannot be executed.
However, of the instructions which are fetched in this manner, some do not require memory access such as an operation between registers and an immediate operation. In this case, since memory competition does not occur, the instruction fetch may be performed during prefetch. However, instruction prefetch is conventionally interrupted even in this case.